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16 v rail-to-rail operational amplifiers ad8565/ad8566/ad8567 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2001C2007 analog devices, inc. all rights reserved. features single-supply operation: 4.5 v to 16 v model ad8565001 operation to 20 v input capability beyond the rails rail-to-rail output swing continuous output current: 35 ma peak output current: 250 ma offset voltage: 10 mv slew rate: 6 v/s unity gain stable with large capacitive loads supply current: 700 a per amplifier applications lcd reference drivers portable electronics communications equipment general description the ad8565/ad8566/ad8567 are low cost, single-supply, rail- to-rail input and output operational amplifiers optimized for lcd monitor applications. they are built on an advanced high voltage cbcmos process. the ad8565 contains a single amplifier, the ad8566 has two amplifiers, and the ad8567 has four amplifiers. these lcd op amps have high slew rates, 35 ma continuous output drive, 250 ma peak output drive, and a high capacitive load drive capability. they have a wide supply range and offset voltages below 10 mv. the ad8565/ad8566/ad8567 are ideal for lcd grayscale reference buffer and v com applications. the ad8565/ad8566/ad8567 are specified over the ?40c to +85c temperature range. the ad8565 single is available in a 5- lead sc70 package. the ad8566 dual is available in an 8-lead msop package. the ad8567 quad is available in a 14-lead tssop package and a 16-lead lfcsp package. pin configurations 1 2 3 5 4 ?in +in v? out v+ ad8565 top view (not to scale) 01909-001 figure 1. 5-lead sc70 pin configuration 45 2 7 36 1 8 out a ?in a +in a v? v+ out b ?in b +in b ad8566 top view (not to scale) 01909-002 figure 2. 8-lead msop pin configuration out b +in b ?in b v+ ?in a +in a out a 8 7 51 0 9 6 4 11 31 2 3 12 1 14 out c +in c ?in c v? ?in d +in d out d ad8567 top view (not to scale) 01909-003 figure 3. 14-lead tssop pin configuration 16 5 13 8 9 12 1 4 1415 2 3 76 11 10 ?in d +in d v? +in c ?in a +in a v+ +in b nc out a out d nc ?in b out b out c ?in c ad8567 top view (not to scale) nc = no connect 01909-004 figure 4. 16-lead lfcsp pin configuration
ad8565/ad8566/ad8567 rev. e | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 pin configurations ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics............................................................. 3 absolute maximum ratings............................................................ 4 thermal resistance ...................................................................... 4 esd caution.................................................................................. 4 typical performance characteristics ............................................. 5 theory of operation .........................................................................9 input overvoltage protection ......................................................9 output phase reversal............................................................... 10 power dissipation....................................................................... 10 thermal padad8567............................................................. 10 total harmonic distortion + noise (thd + n)........................ 11 short-circuit output conditions............................................. 11 lcd panel applications ............................................................ 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 13 revision history 8/07rev. d to rev. e changes to features section............................................................ 1 changes to phase margin ................................................................ 3 changes to table 2............................................................................ 4 changes to figure 30...................................................................... 10 updated outline dimensions ....................................................... 12 changes to ordering guide .......................................................... 13 2/06rev. c to rev. d updated format..................................................................universal changes to figure 6 and figure 8................................................... 5 added the thermal padad8567 section................................ 10 changes to ordering guide .......................................................... 13 3/04rev. b to rev. c changes to specifications ................................................................ 2 changes to tpc 4 ............................................................................. 4 changes to tpc 10........................................................................... 5 changes to tpc 14........................................................................... 6 changes to tpc 20........................................................................... 7 12/03rev. a to rev. b updated ordering guide................................................................. 3 updated outline dimensions ....................................................... 11 10/01rev. 0 to rev. a edit to 16-lead csp and 5-lead sc70 pin configuration ......... 1 edit to ordering guide.................................................................... 3 7/01revision 0: initial version
ad8565/ad8566/ad8567 rev. e | page 3 of 16 specifications electrical characteristics 4.5 v v s 16 v, v cm = v s /2, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit input characteristics offset voltage v os 2 10 mv offset voltage drift v os /t ?40c t a +85c 5 v/c input bias current i b 80 600 na ?40c t a +85c 800 na input offset current i os 1 80 na ?40c t a +85c 130 na input voltage range common-mode input ?0.5 v s + 0.5 v common-mode rejection ratio cmrr v cm = 0 v to v s , ?40c t a +85c 54 95 db large signal voltage gain a vo r l = 10 k, v o = 0.5 v to (v s ? 0.5 v) 3 10 v/mv input impedance z in 400 k input capacitance c in 1 pf output characteristics output voltage high v oh i l = 100 a v s ? 0.005 v v s = 16 v, i l = 5 ma 15.85 15.95 v ?40c t a +85c 15.75 v v s = 4.5 v, i l = 5 ma 4.2 4.38 v ?40c t a +85c 4.1 v output voltage low v ol i l = 100 a 5 mv v s = 16 v, i l = 5 ma 42 150 mv ?40c t a +85c 250 mv v s = 4.5 v, i l = 5 ma 95 300 mv ?40c t a +85c 400 mv continuous output current i out 35 ma peak output current i pk v s = 16 v 250 ma power supply supply voltage v s 4.5 16 v power supply rejection ratio psrr v s = 4 v to 17 v, ?40c t a +85c 70 90 db supply current/amplifier i sy v o = v s /2, no load 700 850 a ?40c t a +85c 1 ma dynamic performance slew rate sr r l = 10 k, c l = 200 pf 4 6 v/s gain bandwidth product gbp r l = 10 k, c l = 10 pf 5 mhz phase margin ? m r l = 10 k, c l = 10 pf 65 degrees channel separation 75 db noise performance voltage noise density e n f = 1 khz 26 nv/hz e n f = 10 khz 25 nv/hz current noise density i n f = 10 khz 0.8 pa/hz
ad8565/ad8566/ad8567 rev. e | page 4 of 16 absolute maximum ratings table 2. parameter rating supply voltage (v s ) 18 v ad8565001 supply voltage (v s ) 20 v input voltage ?0.5 v to v s + 0.5 v differential input voltage v s storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c stresses above those listed u nder absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is no t implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for worst-case conditions, that is, for a device soldered onto a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 5-lead sc70 (ks-5) 376 126 c/w 8-lead msop (rm-8) 210 45 c/w 14-lead tssop (ru-14) 180 35 c/w 16-lead lfcsp (cp-16-4) 38 1 30 1 c/w 1 dap is soldered down to pcb. esd caution
ad8565/ad8566/ad8567 rev. e | page 5 of 16 typical performance characteristics temperature (c) 0 ?0.25 ?1.50 ?40 input offset voltage (mv) ?0.50 ?0.75 ?1.00 ?1.25 v cm = v s /2 v s = 16v 25 85 v s = 4.5v 01909-005 figure 5. input offset voltage vs. temperature frequency (hz) 10 1 0.1 current noise density (pa/ hz) 10 100 1k 10k 4.5v v s 16v t a = 25c 01909-006 figure 6. current noise frequency (1s/div) time (50mv/div) v s = 16v r l = 10k ? c l = 100pf a v = +1 t a = 25c 01909-007 figure 7. small signal transient response 1000 100 1 10 frequency (hz) voltage noise density (nv/ hz) 10 100 1k 10k 4.5v v s 16v t a = 25c 01909-008 figure 8. voltage noise density vs. frequency supply voltage (v) 1.0 0.8 0 supply current/amplifier (ma) 0.6 0.4 0.2 1816141210 86420 v o = v s /2 a v = +1 t a = 25c 01909-009 figure 9. supply current/amplifier vs. supply voltage temperature (c) 0.80 0.75 0.50 supply current/amplifier (ma) 0.70 0.65 0.60 0.55 v cm = v s /2 v s = 16v v s = 4.5v ?40 25 85 01909-010 figure 10. supply current/amplifier vs. temperature
ad8565/ad8566/ad8567 rev. e | page 6 of 16 load capacitance (pf) 100 90 0 overshoot (%) 80 70 60 50 40 30 20 10 ?os +os 10 100 1k v s = 16v v in = 100mv p-p r l = 10k ? a v = +1 t a = 25c 01909-011 figure 11. small signal overshoot vs. load capacitance frequency (hz) output swing (v p-p) 0 2 4 6 8 10 12 14 16 18 10 100 1k 10k 100k 1m 10m v s = 16v a v = +1 r l = 10k ? distortion < 1% t a = 25c 01909-012 figure 12. closed-loop output swing vs. frequency frequency (hz) closed-loop gain (db) 10 20 30 40 50 60 0 10 100 1k 10k 100k 1m 10m 4.5v v s 16v r l = 10k ? c l = 40pf t a = 25c a vcl = ?100 a vcl = ?10 a vcl = +1 01909-013 figure 13. closed-loop gain vs. frequency gain (db) 100 80 60 40 20 frequency (hz) 45 90 135 180 0 225 270 phase shift (degrees) 0 1k 10k 100k 1m 10m 100m 01909-014 v s = 16v r l = 10k ? c l = 40pf t a = 25c figure 14. open-loop gain and phase shift vs. frequency load current (ma) 10 0.1 1 100 1k output vol t age (mv) 0.001 0.01 0.1 1 10 100 t a = 25c v s = 4.5v v s = 16v 01909-015 figure 15. output voltage to supply rail vs. load current temperature (c) 150 output voltage (mv) 135 120 105 90 75 60 45 30 15 0 i sink = 5ma v s = 4.5v v s = 16v ?40 25 85 0 1909-016 figure 16. output voltage swing to rail vs. temperature
ad8565/ad8566/ad8567 rev. e | page 7 of 16 150 output voltage (mv) 135 120 105 90 75 60 45 30 15 0 temperature (c) i source = 5ma v s = 4.5v v s = 16v ?40 25 85 0 1909-017 figure 17. output voltage swing to rail vs. temperature frequency (hz) impedance ( ? ) 500 450 0 400 350 300 250 200 150 100 50 100 1k 10k 100k 1m 10m a v = +1 t a = 25c v s = 4.5v v s = 16v 01909-018 figure 18. closed-loop outp ut impedance vs. frequency frequency (hz) cmrr (db) 20 40 60 80 100 120 0 140 10 100 1k 10k 100k 1m 10m v s = 16v t a = 25c 0 1909-019 figure 19. common-mode rejection ratio (cmrr) vs. frequency power supply rejection r a tio (db) 160 140 ?40 120 100 80 60 40 20 0 ?20 +psrr ?psrr frequency (hz) 100 1k 10k 100k 1m 10m v s = 16v t a = 25c 01909-020 figure 20. power supply reje ction ratio vs. frequency time (40s/div) voltage (3v/div) v s = 16v r l = 10k ? a v = +1 t a = 25c 01909-021 figure 21. no phase reversal input offsetvoltage (mv) 1.8k 1.6k 0 800 600 400 200 1.2k 1.0k 1.4k v s = 16v t a = 25c ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 quantity (amplifiers) 01909-022 figure 22. input offset voltage distribution
ad8565/ad8566/ad8567 rev. e | page 8 of 16 common-mode voltage (v) 7 0 bandwidth (mhz) 6 4 3 2 1 5 0 2 4 6 8 10 12 14 16 v s = 16v a v = +1 r l = x t a = 25c 01909-026 ?5 input offset current (na) ?1 ?2 ?3 ?4 5 1 0 3 2 4 temperature (c) v s = 4.5v v s = 16v ?40 25 85 01909-023 figure 23. input offset current vs. temperature figure 26. frequency vs. common-mode voltage (v s = 16 v) ?350 input bias current (na) ?150 ?200 ?250 ?300 0 ?50 ?100 temperature (c) v s = 4.5v v s = 16v ?40 25 85 v cm = v s /2 01909-024 6 5 0 4 3 2 1 0123 4 5 common-mode voltage (v) bandwidth (mhz) v s = 5v a v = +1 r l = 10k ? t a = 25c 01909-027 figure 24. input bias current vs. temperature figure 27. frequency vs. common-mode voltage (v s = 5 v) c r osstalk (db) ? 20 ?40 ?180 ?60 ?80 ?160 ?100 ?120 ?140 frequency (hz) 50 100 1k 10k 60k 16v 4.5v 0 1909-025 figure 25. channel a vs . channel b crosstalk
ad8565/ad8566/ad8567 rev. e | page 9 of 16 theory of operation the ad8565/ad8566/ad8567 are designed to drive large capacitive loads in lcd applications. they have high output current drive and rail-to-rail input/output operation and are powered from a single 16 v supply. they are also intended for other applications where low distortion and high output current drive are needed. figure 28 shows a simplified equivalent circuit for the ad8565/ ad8566/ad8567. the rail-to-rail bipolar input stage is com- posed of two pnp differential pairs, q4 to q5 and q10 to q11, operating in series with diode protection networks, d1 to d2. diode network d1 to d2 serves as protection against large transients for q4 to q5 to accommodate rail-to-rail input swing. d5 to d6 protect q10 to q11 against zenering. in normal oper- ation, q10 to q11 are off, and their input stage is buffered from the operational amplifier inputs by q6 to d3 and q8 to d4. operation of the input stage is best understood as a function of applied common-mode voltage: when the inputs of the ad8565/ ad8566/ad8567 are biased midway between the supplies, the differential signal path gain is controlled by resistive loads q4 to q5 (via r9, r10). as the input common-mode level is reduced toward the negative supply (v neg or gnd), the input transistor current sources, i1 and i2, are forced into saturation, thereby forcing the q6 to d3 and q8 to d4 networks into cutoff. however, q4 to q5 remain active, providing input stage gain. inversely, when common-mode input voltage is increased toward the positive supply, q4 to q5 are driven into cutoff, q3 is driven into saturation, and q4 becomes active, providing bias to the q10 to q11 differential pair. the point at which the q10 to q11 differential pair becomes active is approximately equal to (v pos ? 1 v). r1 r4 r3 d2 d1 q4 q3 bias line v? d4 d3 q5 q4 q10 q11 c1 c2 d5 d6 q8 q6 r10 r9 folded cascade v + i2 i1 v neg v pos r5 r6 01909-028 figure 28. ad8565/ad8566/ad8567 equivalent input circuit the benefit of this type of input stage is low bias current. the input bias current is the sum of base currents of q4 to q5 and q6 to q8 over the range from (v neg + 1 v) to (v pos ? 1 v). outside this range, the input bias current is dominated by the sum of base currents of q10 to q11 for input signals close to v neg and of q6 to q8 (q10 to q11) for signals close to v pos . from this type of design, the input bias current of the ad8565/ ad8566/ad8567 not only exhibits different amplitude but also exhibits different polarities. figure 29 provides the characteris- tics of the input bias current vs. the common-mode voltage. it is important to keep in mind that the source impedances driving the inputs are balanced for optimum dc and ac performance. input common-mode voltage (v) 02 input bias current (na) 1000 ?1000 800 200 ?200 ?600 ?800 600 400 0 ?400 46810121416 v s = 16v t a = 25c 0 1909-029 figure 29. ad8565/ad8566/ad8567 input bias current vs. common-mode voltage to achieve rail-to-rail output performance, the ad8565/ ad8566/ad8567 design uses a complementary common- source (or gmrl) output. this con-figuration allows output voltages to approach the power supply rails, particularly if the output transistors are allowed to enter the triode region on extremes of signal swing, which are limited by v gs , the transistor sizes, and output load current. in addition, this type of output stage exhibits voltage gain in an open-loop gain configuration. the amount of gain depends on the total load resistance at the output of the ad8565/ad8566/ad8567. input overvoltage protection as with any semiconductor device, whenever the input exceeds either supply voltages, attention needs to be paid to the input overvoltage characteristics. as an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the magnitude of the fault current. when the input voltage exceeds either supply by more than 0.6 v, internal positive-negative (pn) junctions allow current to flow from the input to the supplies.
ad8565/ad8566/ad8567 rev. e | page 10 of 16 this input current is not inherently damaging to the device as long as it is limited to 5 ma or less. if a condition exists using the ad8565/ad8566/ad8567 where the input exceeds the supply more than 0.6 v, an external series resistor should be added. the size of the resistor can be calculated by using the maximum over-voltage divided by 5 ma. this resistance should be placed in series with either input exposed to an overvoltage. output phase reversal the ad8565/ad8566/ad8567 are immune to phase reversal. although device output does not change phase, large currents due to input overvoltage could damage the device. in applica- tions where the possibility of an input voltage exceeding the supply voltage exists, overvoltage protection should be used as described in the input overvoltage protection section. power dissipation the maximum allowable internal junction temperature of 150c limits the maximum power dissipation of ad8565/ ad8566/ad8567 devices. as the ambient temperature increases, the maximum power dissipated by ad8565/ad8566/ ad8567 devices must decrease li nearly to maintain maximum junction temperature. if this maximum junction temperature is exceeded momentarily, the device still operates properly once the junction temperature is reduced below 150c. if the maximum junction temperature is exceeded for an extended period, overheating could lead to permanent damage of the device. the maximum safe junction temperature, t jmax , is 150c. using the following formula, the maximum power that an ad8565/ ad8566/ad8567 device can safely dissipate as a function of temperature can be obtained: p diss = t jmax ? t a / ja where: p diss is the ad8565/ad8566/ad8567 power dissipation. t jmax is the ad8565/ad8566/ad8567 maximum allowable junction temperature (150c). t a is the ambient temperature of the circuit. ja is the ad8565/ad8566/ad8567 package thermal resistance, junction-to-ambient. the power dissipated by the device can be calculated as p diss = ( v s ? v out ) i load where: v s is the supply voltage. v out is the output voltage. i load is the output load current. figure 30 shows the maximum power dissipation vs. temper- ature. to achieve proper operation, use the previous equation to calculate p diss for a specific package at any given temperature or use figure 30 . ambient temperature (c) 1.25 0.75 0 ?35 maximum power dissip a tion (w) 0.50 0.25 1.00 ?15 5 25 45 65 85 16-lead lfcsp 5-lead sc70 8-lead msop 14-lead tssop 01909-030 figure 30. maximum power dissipation vs. temperature for 5-lead sc70, 8-lead msop, 14-lead tssop, and 16-lead lfcsp packages thermal padad8567 the ad8567 lfcsp comes with a thermal pad that is attached to the substrate. this substrate is connected to v dd . to be electrically safe, the thermal pad should be soldered to an area on the board that is electrically isolated or connected to v dd . attaching the thermal pad to ground adversely affects the performance of the part. soldering down this thermal pad dramatically improves the heat dissipation of the package. it is necessary to attach vias that connect the soldered thermal pad to another layer on the board. this provides an avenue to dissipate the heat away from the part. without vias, the heat is isolated directly under the part.
ad8565/ad8566/ad8567 rev. e | page 11 of 16 total harmonic distortion + noise (thd + n) lcd panel applications the ad8565/ad8566/ad8567 feature low total harmonic dis- tortion. figure 31 shows thd + n vs. frequency. the thd + n over the entire supply range is below 0.008%. when the device is powered from a 16 v supply, the thd + n stays below 0.003%. figure 31 shows the ad8566 in a unity noninverting configuration. the ad8565/ad8566/ad8567 amplifier is designed for lcd panel applications or applications where large capacitive load drive is required. it can instantaneously source/sink greater than 250 ma of current. at unity gain, it can drive 1 f without compensation. this makes the ad8565/ad8566/ad8567 ideal for lcd v com driver applications. frequency (hz) 20 thd+n (%) 100 10 1 0.01 0.1 1k 10k 30k v s = 2.5v v s = 8v 01909-031 to evaluate the performance of the ad8565/ad8566/ad8567, a test circuit was developed to simulate the v com driver application for an lcd panel. figure 32 shows the test circuit. series capacitors and resistors connected to the output of the op amp represent the load of the lcd panel. the 300 and 3 k feedback resistors are used to improve settling time. this test circuit simulates the worst-case scenario for a v com . it drives a represented load that is connected to a signal switched symmet- rically around v com . figure 33 shows a scope photo of the instantaneous output peak current capability of the ad8565/ad8566/ad8567. input 0v to 8v square wave with 15.6s pulse width 300? 3k ? 10? 10? 10? 10? 10nf 10nf 10nf 10nf measure current 4v 8v 10? to 20 ? 01909-032 figure 31. thd + n vs. frequency short-circuit output conditions the ad8565/ad8566/ad8567 do not have internal short- circuit protection circuitry. as a precautionary measure, it is recommended not to short the output directly to the positive power supply or to ground. figure 32. v com test circuit with supply voltage at 16 v it is not recommended to operate the ad8565/ad8566/ad8567 with more than 35 ma of continuous output current. the output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using time (2s/div) 0 1909-033 ch 2 = 100ma/div ch 1 = 5v/div 10 0% 100 90 ma35 s x v r for a 5 v single-supply operation, r x should have a minimum value of 143 . figure 33. scope photo of the v com instantaneous peak current
ad8565/ad8566/ad8567 rev. e | page 12 of 16 outline dimensions compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 34. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters compliant to jedec standards mo-203-aa 0.30 0.15 0 . 1 0 m a x 1.00 0.90 0.70 0.46 0.36 0.26 seating plane 0.22 0.08 1.10 0.80 4 5 123 pin 1 0.65 bsc 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 0.10 coplanarity 0.40 0.10 figure 35. 5-lead thin shrink small outline transistor package [sc70] (ks-5) dimensions shown in millimeters 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-ab-1 figure 36. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters
ad8565/ad8566/ad8567 rev. e | page 13 of 16 compliant to jedec standards mo-220-vggc 2 . 2 5 2 . 1 0 s q 1 . 9 5 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indicator top view 4.00 bsc sq 3.75 bsc sq coplanarity 0.08 (bottom view) 12 max 1.00 0.85 0.80 seating plane 0.35 0.30 0.25 0.80 max 0.65 typ 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indicator 0.25 min 021207-a 0.75 0.60 0.50 figure 37. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-4) dimensions shown in millimeters ordering guide model abs max (v) temperature range package description package option branding ad8565001aksz-r2 1 20 ?40c to +85c 5-lead thin shrink small outline transistor package (sc70) ks-5 l7l ad8565001aksz-reel7 1 20 ?40c to +85c 5-lead thin shrink small outline transistor package (sc70) ks-5 l7l ad8565aks-r2 18 ?40c to +85c 5-lead thin shrink small outline transistor package (sc70) ks-5 asa AD8565AKS-REEL7 18 ?40c to +85c 5-lead thin shrink small outline transistor package (sc70) ks-5 asa ad8565aksz-reel7 1 18 ?40c to +85c 5-lead thin shrink small outline transistor package (sc70) ks-5 a0n ad8566arm-r2 18 ?40c to +85c 8-lead mini small outline package (msop) rm-8 ata ad8566arm-reel 18 ?40c to +85c 8-lead mini small outline package (msop) rm-8 ata ad8566armz-r2 1 18 ?40c to +85c 8-lead mini small outline package (msop) rm-8 ata# ad8566armz-reel 1 18 ?40c to +85c 8-lead mini small outline package (msop) rm-8 ata# ad8567aru 18 ?40c to +85c 14-lead thin sh rink small outline package (tssop) ru-14 ad8567aru-reel 18 ?40c to +85c 14-lead thin shrink small outline package (tssop) ru-14 ad8567aruz 1 18 ?40c to +85c 14-lead thin shrink small outline package (tssop) ru-14 ad8567aruz-reel 1 18 ?40c to +85c 14-lead thin shrink small outline package (tssop) ru-14 ad8567acp-r2 18 ?40c to +85c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-4 ad8567acp-reel 18 ?40c to +85c 16-lead lead frame ch ip scale package (lfcsp_vq) cp-16-4 ad8567acp-reel7 18 ?40c to +85c 16-lead lead frame ch ip scale package (lfcsp_vq) cp-16-4 ad8567acpz-r2 1 18 ?40c to +85c 16-lead lead frame ch ip scale package (lfcsp_vq) cp-16-4 ad8567acpz-reel 1 18 ?40c to +85c 16-lead lead frame ch ip scale package (lfcsp_vq) cp-16-4 ad8567acpz-reel7 1 18 ?40c to +85c 16-lead lead frame ch ip scale package (lfcsp_vq) cp-16-4 1 z = rohs compliant part; # denotes lead-free product may be top or bottom marked.
ad8565/ad8566/ad8567 rev. e | page 14 of 16 notes
ad8565/ad8566/ad8567 rev. e | page 15 of 16 notes
ad8565/ad8566/ad8567 rev. e | page 16 of 16 notes ?2001C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c01909-0-8/07(e)

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